1. Field of the Invention
This invention relates generally to the transfer of data over a network communication link. In particular, the present invention relates to methods of synchronizing a network communication link for transferring data.
2. Description of the Related Art
Data networks can use either shared buses or a channel-oriented fabric of switchable point-to-point serial links. The channel-oriented switched fabric architecture is designed to address the problems of I/O reliability, scalability, modular packaging, performance and complexity in commercial high-volume servers. It uses an efficient I/O channel engine which is decoupled from the CPU system and which can independently transfer network data to and from main memory.
One challenge to implementing a data network which utilizes a channel-oriented, switched fabric, serial link architecture is to ensure that the high-speed data communications between a data transmitter (source node) and a data receiver (destination node) operating in two different clocks are synchronous with respect to the transmission and reception of data within each data packet. Such data transmitter and data receiver may correspond to different network nodes (end stations such as host computers, servers, and/or I/O devices) and operate in synchrony with different clock signals. Failure to maintain synchronization between the data transmitter and data receiver may result in the miscommunication (data corruption) and therefore, effective loss of data.
As shown in FIG. 1, a network interface controller (NIC) has both a transmitter and a receiver. Each NIC in FIG. 1 has only a single transmitter/receiver pair. However, a NIC can have any number of such pairs (“ports”) supporting respective links. Link synchronization is the process of synchronizing the transmitters and receivers on each end of a serial link. Prior to link establishment, a transmitter is under the control of that port's receiver. The receiver essentially determines the necessary transmission sequence based on the data received on the link.
One common link synchronization method uses IDLE sequences. Specifically, a first device initiates the process by transmitting IDLE-1 characters to a second device until 3 consecutive IDLE-1 characters are received. At that time, the device transmits IDLE-2 characters until a single IDLE-2 character is received. Upon reception of the IDLE-2 character, link is determined to be synchronized and therefore established. At the point where link is determined to be established, the corresponding receiver no longer controls the transmitter and transmit data becomes a function of the transmit state machine.
FIG. 2 depicts the interaction between a NIC transmitter and receiver pair for link synchronization. The receiver is divided into receiver and physical (PHY) blocks based on clock source. The PHY block receives the RXCLK clock signal from the SERDES and operates in the RXCLK domain. The receiver and transmitter blocks both receive a Core Clk signal from the silicon core and function in the core clock domain. The XMIT_I1 and XMIT_I2 control signals signify to the transmitter which synchronization character (Idle-1 or Idle-2) requires transmission in order to establish link. The Link_Good signal indicates when the serial link has been synchronized (established) and the transmitter then assumes control of the transmit data stream.
Since the Link Synchronization machine resides in the PHY block, the three generated sideband signals are asynchronous to the core clock domain in which the transmitter operates. In order to effectively sample these control signals in the core clock domain, the transmitter must implement synchronizers to pass the information into this asynchronous clock domain. These synchronizers add additional hardware to the device and pose a significant issue during synthesis. In addition, these asynchronous control signals and their associated synchronizers interfere with the normal functionality of the transmitter, and are difficult to synthesize and debug.